1. Field of the Invention
This invention relates generally to differential to single-ended converter circuits and more particularly to a differential to single-ended converter circuit which utilizes integrated injection logic techniques.
2. Description of the Prior Art
Bipolar differential input comparator circuits are well known in the integrated circuit field. Generally a comparator circuit functions to indicate whether the voltage applied to a first input is above or below the voltage applied to a second input. The differential input voltage is coupled to an emitter coupled pair of transistors, the collectors of which provide differential current drive to a differential to single-ended converter circuit.
Integrated circuit technology has advanced to the extent that analog and digital functions are often fabricated as a single integrated circuit providing an entire system on a single chip. Integrated injection logic (I.sup.2 L) is well known in the prior art for providing digital logic functions with increased device densities and reducing chip area. Circuits which combine bipolar analog circuitry with I.sup.2 L digital circuitry are known in the art. However the linear portions of prior art circuitry are generally constructed by using conventional NPN and PNP transistors, each employing an epitaxial region which is electrically isolated by a reverse-biased junction from the epitaxial regions used to form other transistors. Generally, the electrical isolation is achieved by diffusing a heavily-doped P-type isolation diffusion into an epitaxial region, thereby forming isolated epitaxial islands. Thus, prior art circuits which have combined analog and digital functions on a single integrated circuit chip have utilized integrated injection logic primarily within the digital portions of the chip. It is therefore easily appreciated by those skilled in the art that the use of integrated injection logic structures in the analog portions of the chip will realize a significant savings in chip area.
Furthermore, at the interface between the analog and digital portions of the circuit, it is desirable that the output from the analog circuitry be compatible with the input of the digital circuitry. It will therefore be appreciated by those skilled in the art that a differential to single-ended converter circuit providing multiple collector outputs adapted for directly driving I.sup.2 L gates is a significant improvement over the prior art.
An ideal comparator circuit having zero offset will cause the single-ended output to switch when the differential input voltage is zero, i.e., when the first input voltage and the second input voltage are equal. It is desirable to maintain the comparator offset at a minimum despite changes in temperature in a given chip or changes in processing from one chip to another. Because conventional NPN and PNP transistors have different characteristics from I.sup.2 L devices, the parameters for conventional transistors vary in a different manner from the variation in the parameters of I.sup.2 L devices when a circuit is subjected to changes in temperature or processing. Therefore, it should be appreciated by those skilled in the art that a differential to single-ended converter circuit which interfaces directly to I.sup.2 L circuitry and which minimizes the offset associated with a comparator circuit despite changes in temperature or processing is a significant improvement over the prior art.